This invention relates to methods and apparatus for detecting defect-densities in a semiconductor integrated circuit product and/or test structure to thereby predict product-limited yields and the product lot yields. More particularly, it relates to mechanisms for determining critical area, which is a necessary parameter for, among many purposes including prediction of the end-of-line product yield from the in-line testing and/or inspection database.
Conventionally, the test structures on a test wafer or product wafer are inspected or tested for defects, more specifically for electrical fails. The resulting defect sample may then be used to predict the yield of a product wafer lot. The test structures may be inspected using either an optical inspection tool or a scanning electron microscope. In an optical inspection, a beam of light is directed towards the test structures and the scattered light is then analyzed to determine whether defects are present within the test structures.
Another type of inspection is referred to as a voltage contrast inspection, using a scanning electron microscope. The voltage contrast technique operates on the basis that potential differences in the various conductive shapes of a sample under examination cause differences in, typically, the secondary and/or backscattered electron emission intensities when the sample is the target of a low-energy and high-current electron beam. The potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a lower potential portion might be displayed as dark and a high potential portion might be displayed as bright.
An electron detector is used to measure the intensity of the secondary electron emission that originates from the path swept by the scanning electron beam. Images may then be generated from these electron emissions. A defective portion can be identified from the potential state or appearance of the portion under inspection. The test structure portion under inspection is typically designed to produce a particular potential and resulting brightness level in an image during the voltage contrast inspection. Hence, when the scanned portion's potential and resulting image appearance differs significantly from the expected result, the scanned portion is classified a defect.
Several inventive test structures designed by the present assignee are disclosed in U.S. Pat. No. 6,433,561 by Akella V. S. Satya et al., issued 13 Aug. 2002, which application is incorporated herein by reference in its entirety. One test structure is designed to have alternating high and low potential conductive lines during a voltage contrast inspection. In one inspection application, the low potential lines are at ground potential, while the high potential lines are at a floating potential. However, if a line that is meant to remain floating shorts to an adjacent grounded line, both lines will then produce a low potential during a voltage contrast inspection. If there is an open defect present within a line that is designed to be coupled to ground, this open will cause a portion of the line to be left at a floating potential to thereby produce a high potential during the voltage contrast inspection. Both open and short defects cause two adjacent lines to have the same potential during the voltage inspection.
The results from inspecting the test structures, typically in a test chip, may then be used to the predict yield of a product chip that is fabricated with the same process as the test chip. Such chip yield is generally a product of the product-limited yields for all the primary defect mechanisms predicted from the corresponding test-structure yields. Each test structure yield is generally a function of the product of the defect density of the process and the critical area of such particular test structure. That is, given a particular defect is present in the test chip, the probability that the test structure will fail depends on the critical area of the test structure. Critical area refers to the fractional area of the chip-layout window, in which if a defect occurs, it would cause a fault (e.g., an electrical fail due to a short or an open). Each specific configuration of semiconductor circuit, pattern, and test structure has an associated critical area. Additionally, each specific circuit, pattern, and test structure has an associated Probability of fail curve as a function of defect size.
FIGS. 1A and 1B illustrate the concept of critical area. FIG. 1A is a diagrammatic top view of a simple test structure 100 having two conductive lines 102a and 102b. The lines 102a and 102b both have a width 104 and a spacing 106. FIG. 1B is a graph showing the critical area 103, the probability of fail 105 and the defect-size distribution 107 [normalized to unity between Xo and ∞] as a function of defect size for the test structure 100 of FIG. 1A. A defect 110 that has a size less than the line spacing will not cause a fault (e.g., short) in any area of test structure 100. As shown in FIG. 1B, the probability of fail is zero for defects of sizes less than the line-width 106. However, a defect 108 having a size (e.g., diameter) equal to or greater than the width 106 will have an associated probability for causing a fault. For example, if the center of the defect 108 is positioned in a narrow area 109 that runs down the centerline between the two lines 102, it will cause a fault by shorting the two lines 102. The ratio of this narrow area 109 and the area of the window 100 is the probability of fail for defect 108. The probability of fail will continue to increase for increasingly sized defects until it equals unity at a particular defect size. For this test structure 100, the plateau at unity occurs at a defect size that is twice the width of the line 104 plus the spacing 106. When this probability of fail curve 105 is convoluted with the defect-size distribution 107 and the result is integrated between the limits of Xo and Xmax, a reasonably large [maximum] defect size much greater than [(2*104)+(106)], the critical area may be obtained.
One conventional technique implements a closed-form solution for the probability of fail curve for the conductive line structures each having a width W, and separated by a distance S: The probability of fail is:                               PoF          ⁢                      {            X            }                          =        0                                      for          ⁢                                           ⁢          X                ≤                  (          106          )                                                  PoF          ⁢                      {            X            }                          =                              X            -            S                                W            +            S                                                                    for            ⁢                                                   ⁢                          (              106              )                                <          X          <                      [                                          2                *                                  (                  104                  )                                            +                              (                106                )                                      ]                          ,        and                                          PoF          ⁢                      {            X            }                          =        1                                                  for            ⁢                                                   ⁢            X                    ≥                      [                                          2                *                                  (                  104                  )                                            +                              (                106                )                                      ]                          ;            and the Critical Area is:                     CA        =                ⁢                              ∫                          X              0                                      X              max                                ⁢                      PoF            ⁢                                          {                X                }                            ·              DSD              ·                              ⅆ                x                                                                            =                ⁢                                            (                              p                -                1                            )                                      (                              p                -                1                            )                                *                                                ⁢                              X            0                    ⁡                      [                                                            ∫                                      X                    0                                                                              2                      *                      S                                        +                    W                                                  ⁢                                                      (                                                                  X                        -                        S                                                                    W                        +                        S                                                              )                                    *                                      (                                          1                      /                                              X                        p                                                              )                                    ⁢                                      ⅆ                    X                                                              +                                                ∫                                                            2                      *                      S                                        +                    W                                                        X                    max                                                  ⁢                                                      1                    /                                          X                      p                                                        ⁢                                      ⅆ                    x                                                                        ]                              
However, this closed-form solution is only valid for parallel lines of one constant width and spacing, which is neither typical in any product, nor in a usual test structure layout.
One conventional technique for determining critical area is referred to as the “Quasi-Monte Carol simulation.” In this technique, random defects are simulated as being superimposed on a particular design data. These simulated defects initially have a particular diameter x. The number of faults produced by these defects having an initial diameter x is then determined. Defects having a diameter equal to x+Δx are then simulated on the design data.
The number of a faults is then determined for defects having the diameter x+Δx. This simulation process iteratively repeats for larger sized defects until a maximum defect size of Xmax is reached. The probability of fail can then be determined from the number of faults and the total number of defects simulated at each incremental Δx step. This iterative process is very time consuming, even for one defect mechanism (such as opens or shorts).
In another technique, each design structure is incrementally expanded until a short fault occurs when the two structures short together. The distance that the structure expanded is equal to the radius of the defect that can cause a fault. Similarly, for the case of the opens, the shapes are contracted by Δx iteratively for determining the probability of fail curve [until Xmax.] Although these techniques all succeed in determining critical area for a particular structure type, these conventional simulation techniques are each very time consuming and utilize a significant amount of processor and memory resources. Other techniques perform a simulation on “sample” portions of the design data, rather than the entire design data. One example of a critical area determination software tool is EYES developed at the University of Edinburgh, England. However, this technique may produce inaccurate determinations of the critical areas, if the simulation sampling does not include representative portions of the critical design regions of the design.
Accordingly, methodologies for more efficiently and accurately determining the critical area for a particular test structure or a product design are needed.